In recent years, problems have been posed by intersymbol interference (ISI) due to signal attenuations on PCBs (Printed Circuit Boards) for high-speed signal transmission such as interchip serial data communications or the like. As shown in FIG. 1, ISI is a phenomenon wherein when a transmitted 1-bit signal is received, its waveform is deformed into a tail that tends to interfere with successive bits. Heretofore, it has been the prevailing practice to suppress interferences by using waveform equalizing technology incorporated in transmitting circuits. However, it has become difficult for the waveform equalization in transmitting circuits to achieve highly accurate waveform equalization control for handling large signal attenuations.
Waveform equalization in a transmitting circuit is controlled by its waveform equalization coefficient, which is set to an optimum value based on the reception result at a receiving circuit. Therefore, the receiving circuit has to transmit the reception result to the transmitting circuit, and needs a transmission mechanism. Furthermore, as the communication rate increases, the band of the data signal increases, and hence the number of successive bits (postcursors) affected by ISI also increases (see FIG. 1). As a result, the ISI of these cursors also has to be controlled, and optimum waveform equalization cannot be achieved by only the waveform control quantity which the transmitting circuit can provide.
For the above reasons, high-speed signal transmission in recent years has seen a growing demand for waveform equalization in receiving circuits. As a result, much waveform equalization is being performed by decision feedback equalizers. The decision feedback equalizer adds a control quantity for correcting ISI from a past signal in superimposed relation to a present received signal D(n) for the equalization of the signal waveform. For example, an ISI quantity that is applied to a first postcursor by means of preceding signal D(n−1) is controlled and extracted from present signal D(n), thereby removing the effect that the ISI has on preceding signal D(n−1). At the same time, an ISI quantity that is applied to a second postcursor by means of signal D(n−2) which is two bits prior to present signal D(n) is controlled and extracted from present signal D(n), thereby removing the effect that the ISI has on signal D(n−2). Generally, immediately preceding bit D(n−1) imposes the greatest ISI on present received signal D(n). In other words, correcting the first postcursor of each data is highly effective in waveform equalization.
FIG. 2 is a block diagram of a general decision feedback equalizer which employs a full-rate clock. A signal that is transmitted from transmitting circuit 100 is received by amplifying circuit 1 in receiving circuit 102′ via transmission path 101. Amplifying circuit 1 has a feature, for example, that it has a high-impedance input terminal provided by the gate terminal of a transistor. Amplifying circuit 1 provides an output signal to controlled terminal 2. D flip-flop DFF4-1 receives the output signal to determine whether the signal is binary data “1” or “−1”. The D flip-flop DFF, as described herein, may be a general DFF or a signal detecting circuit for determining and holding data in synchronism with a clock such as a sampling latch signal. The determined data are successively shifted to D flip-flops DFF4-2 through DFF4-n in synchronism with the clock. Output signals h1 through hn from the D flip-flops are applied to respective current control blocks 3-1 through 3-n (CCB1 through CCBn), which control controlled terminal 2 to equalize the waveform at controlled terminal 2. For example, if past determined data hn represents “1”, then its ISI appears in a postcursor, and appears in the present input signal which is n bits later. The ISI of the past data needs to be canceled for waveform equalization. Therefore, if hn represents “1”, then a controlled current from current control block 3-n is fed back to controlled terminal 2, canceling postcursor ISI due to data “1” which is n bits earlier. Thus, ISI on the present data can be canceled by past received data for waveform equalization. Since ISI is determined as being present or not depending on whether past determined data h1 through hn are “1” or “−1”, controlled terminal 2 is adaptively controlled by h1 through hn for each bit.
The decision feedback controller shown in FIG. 2 operates under such conditions that total time Δtdfe of a data decision delay time of D flip-flop DFF4-1 (DFF delay time, etc.), a time for completing the control of controlled terminal 2 by current control block CCB1, and a preparation time (setup time) for receiving next time is smaller than time ΔT until next data arrive (bit period, e.g., 100 psec. for 100 bps). However, since bit period ΔT becomes smaller as the communication rate increases, allowable time of Δtdfe becomes shorter. Consequently, as there is no negative feedback time for immediately preceding data, a problem associated with high-rate communications arises in that it is difficult to cancel the ISI on the first postcursor, making it impossible to perform waveform equalization.
To address the above problem, Non-patent document 1 discloses an equalizer called a loop unrolled DFE/speculative DFE. This document handles the above problem as follows:
FIG. 3 shows an example of a loop unrolled DFE/speculative DFE. In this system as well, ISI which is imposed on present data and which is caused by data that are two bits or more prior to the present data is canceled by current control based on past decision data as with the DFE shown in FIG. 2. Therefore, D flip-flop DFF4-2 and subsequent D flop-flops are identical in arrangement to those of the equalizer shown in FIG. 2, and ISI on the second and subsequent postcursors at controlled terminal 2 is canceled out. The loop unrolled DFE/speculative DFE is different from the equalizer shown in FIG. 2 as to the arrangement for canceling ISI on the first postcursor which is responsible for the above problem. According to this system, unlike the equalizer shown in FIG. 2, decision data h1 is not fed back for canceling ISI on the first postcursor. In the loop unrolled DFE/speculative DFE shown in FIG. 3, two parallel amplifying circuits 5, 6 are connected to controlled terminal 2. Amplifying circuits 5, 6 have output terminals respectively as controlled terminals 7, 8 that are current-controlled by respective current control blocks CCB1+, CCB1−. Current control block CCB+ controls controlled terminal 7 with a current on the assumption that data that is one bit earlier represents “1”. Current control block CCB− controls controlled terminal 8 with a current on the assumption that data that is one bit earlier represents “−1”. This means that the data that is one bit earlier is speculatively decided. The signals from controlled terminals 7, 8 are input respectively to D flop-flops DFF4-1+, DFF4-1−, which speculatively determine the data. Output signals from D flop-flops DFF4-1+, DFF4-1− are input to elector circuit SEL, which selects a speculatively determined result based on the determined value of output signal h2 from D flip-flop DFF4-2 that represents the determined data which is determined one bit earlier than h1. The above description represents the arrangement and operating principle of the loop unrolled DFE/speculative DFE. Since there is no feedback path for feeding immediately preceding data h1 back to the present data, the problem of the feedback time of h1 is eliminated.    Non-patent document 1: M. Sorna, et al., “A 6.4 Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers San Francisco, Calif., February 2005. pp. 62-63.